The present invention relates to digital logic circuits. In particular, the present invention relates to a multi-input, compound function noise-immune logic circuit.
In the field of integrated circuit design, Emitter-Coupled Logic (ECL) and Complementary Metal-Oxide-Semiconductor logic (CMOS) are the most popular logic families used at present.
ECL offers high-speed operation but large systems are difficult to design successfully using ECL because of its large power dissipation, limited logic functionality, and poor noise immunity, which can compromise the operational reliability of the overall system.
By comparison, CMOS consumes less power but yields somewhat lower speeds than ECL. Because of the highly interconnected and redundant nature of fully complementary static CMOS logic designs, CMOS integrated circuits are frequently implemented with dynamic-CMOS logic-gate design techniques that inherently trade off operational reliability in an attempt to circumvent the somewhat restricted logic functionality of the CMOS logic family.
Prior-art logic families suffer from sacrificed operational reliability, limited logic functionality, and nonuniform propagation delays within each logic family. These nonuniform delays make it virtually impossible to design a large-scale system that does not have to be redesigned because of critical-speed paths that fail to meet their timing windows, and thereby cause the system to malfunction.
U.S. Pat. Nos. 4,853,561 and 4,868,904 for Noise-Immune Logic (NIL) and Complementary Noise-Immune Logic (CNIL), respectively, teach the use of interacting constant-voltage and constant-current elements in digital logic gates.